1. Field of the Invention
The present invention relates to a reset circuit that short-circuits an output voltage terminal of a power IC to a GND level in a standby mode in the case where the power IC which generates a voltage lower than VSS has the standby mode where the operation of an internal circuit stops in order to reduce power consumption.
2. Description of the Related Art
In general, positive and negative bias power supplies are required in order to drive a liquid crystal display panel (hereinafter referred to as xe2x80x9cLCD panelxe2x80x9d). In the case where the LCD panel is mounted on a portable equipment, a power IC such as a switching regulator or a charge pump circuit is used in order to boost a voltage of a battery to a voltage required for the LCD panel or to develop a reverse voltage. Then, in order to elongate the operating lifetime of the battery mounted on the portable equipment, a demand is made in which the power IC is provided with a standby mode where the operation of the internal circuit is completely stopped when display of the LCD is not necessary.
In this situation, when the internal circuit of the power IC stops to operate, charges remaining in a capacitor connected to an output terminal of the power IC are reduced due to leakage, to thereby gently reduce the output voltage. However, when the output voltage of the power IC remains for a long period of time, there arises such a problem that an excessive load is given to the LCD panel, which is not preferable in reliability.
Under the above circumstance, as means for solving the above problem, there has been proposed a method in which a MOS switch is connected between the output terminal and the GND, and the MOS switch is turned on to shortcircuit the output terminal to the GND level, to thereby discharge the residual charges in the capacitor in a short period of time.
In the case where the output voltage of the power IC is lower than a supply voltage VSS which is a lower one of two supply voltages of the IC, the MOS switch cannot be realized on the IC. The reason is that if the MOS switch is going to be realized by an n-channel transistor, because a parasitic p-n junction diode always turns on in a p-type substrate of the VSS level and an n+ region lower in potential than VSS, the output voltage of the power IC is fixed to a voltage lower than the VSS level by the forward on-state voltage of the diode.
On the other hand, if the MOS switch is going to be realized by a p-channel transistor, when the gate voltage of the p-channel transistor is controlled by the level of two supply voltages VDD and VSS of the IC, the p-channel transistor always turns off without the gate voltage being smaller than the source voltage (VSS level).
Also, even if an external n-channel transistor is used, if two supply voltages VDD and VSS of the IC are used to control the gate voltage of the transistor, the transistor always turns on with the result that the on/off operation cannot be controlled.
On the other hand, even if an external p-channel transistor is used, if two supply voltages VDD and VSS of the IC are used to control the gate voltage of the transistor, the transistor always turns off with the result that the on/off operation cannot be controlled.
As described above, there arises such a problem that the on/off operation of the MOS switch cannot be controlled, in the standby mode in which the power IC that generates a voltage lower than VSS stops the operation of the internal circuit, the MOS switch is used to shortcircuit the output voltage terminal of the power IC to the GND level, and two supply voltages VDD and VSS are used to control the gate voltage of the MOS switch.
The present invention has been made to solve the above problem, and therefore an object of the present invention is to provide a reset circuit which is simple in circuit structure and is capable of reducing the costs.
Another object of the present invention is to provide a reset circuit which is capable of suppressing a current consumption to a minimum.
Still another object of the present invention is to provide a reset circuit which is capable of surely controlling the on/off operation of the MOS switch.
In order to achieve the above objects, according to the present invention, there is provided a reset circuit structured such that an invertor including one p-channel transistor which is an external part, one n-channel transistor which is an external part and one resistor which is an external part is operated by a positive supply voltage (VDD) and a negative voltage generated by a reverse switching regulator.
Also, according to the present invention, there is provided a reset circuit in which a current is only the though-current that flows through the invertor as soon as the mode is switched over.
Also, according to the present invention, there is provided a reset circuit in which a MOS switch is controlled by a comparator circuit and a reference voltage to shortcircuit the negative output voltage terminal of the power IC to the GND level. In the reset circuit thus structured, the negative supply voltage of the comparator circuit is applied from the negative output voltage of the power IC whereby the amplitude of the output voltage of the comparator circuit is expanded from VDD to the level of the negative output voltage of the power IC.